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| SHOWCASE
— THE 2003 ITRS TECHNOLOGY WORKING GROUP MODELS |
The 2003 ITRS supplemental files’ links
include a variety of models that extrapolate the technology
requirements. These links also include files that provide more
detail about potential solutions or areas for innovation.
While these links are located throughout the chapters in context
to the subject matter, for your convenience we have also compiled
these links on this page, as related to their associated chapters. |
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SYSTEM DRIVERS AND DESIGN
The GSRC Technology Extrapolation (GTX) system
has been developed with the goals of flexibility, quality
and prevention of redundant effort in mind. The GTX system
addresses these goals by providing an open, portable framework
for specification and comparison of alternative modeling choices.
GTX
model
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PROCESS INTEGRATION
Logic models
low operating power (LOP), low standby power (LSTP), and high
performance (HP) devices
For generating the entries in the logic technology
requirements tables, an approach was used in which simplified
models were created and embedded in a spreadsheet. These models
capture the essentials of the impact of such key input parameters
as the power supply voltage, (Vdd), equivalent
oxide thickness (EOT), gate length, etc., on the important
transistor electrical output characteristics such as leakage
current, saturation drive current, etc.
An important calculated output parameter is the intrinsic
MOSFET delay, t = CV/I, where C
is the total gate capacitance (including parasitic gate overlap
and fringing capacitance) per micron transistor width, V is
Vdd, and I is the saturation drive current per
micron transistor width, Id,sat. t
is a good metric for the intrinsic MOSFET delay, and hence
1/t is a good metric for the maximum
intrinsic MOSFET switching frequency. 1/t
is used as the key transistor performance metric. To determine
the projected parameter values in a table, a target is set
for one of the key outputs, such as leakage current or 1/t.
Then the input parameters are tentatively chosen based on
scaling rules, engineering judgment, and physical device principles.
The spreadsheet capabilities are used to iteratively vary
the input parameters until the target is met, and the final
set of values for the input parameters is entered into the
table. The specific set of projected parameter values in each
of the tables reflects a particular scaling scenario, in which
the targeted values for the key output are achieved.
Low
Operation Power Model
Low
Standby Power Model
High
Perfomance Model
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EMERGING RESEARCH DEVICES
MASTAR application
Mastar 2.0 is a computing tool especially
conceived for the calculation of the electrical characteristics
of advanced CMOS devices such as planar bulk transistors,
Double Gate (DG) or Silicon On Isolator (SOI) devices. The
calculation is based on analytical drift diffusion equations,
which depend directly on the major technological parameters,
such as gate length, channel doping, oxide thickness, etc.
This application allows the user to evaluate immediately the
impact of these technological parameters on the main transistor
characteristics such as the threshold behavior, performance
values or time delay. Moreover, the influence of “physical”
secondary parameters such as mobility, poly depletion and
dark space can be visualized giving a deep insight in the
physics of CMOS devices. Due to a possible limited validity
of the drift diffusion models with respect to very short devices,
the MASTAR predictions should be considered as “worst
case”.
Downloadable
MASTAR .zip File - RIGHT CLICK to
save the zip file to your hard drive.
The installation of the
MASTAR 2.0 package
Mastar 2.0 is delivered as a compressed package
of files. After reception, please create a MASTAR folder where
you copy the whole stack of files. For execution, just click
on the MASTAR 2.0.exe file. Whenever you create or modify files
(e. g. profile files, plot files or result files) within MASTAR
2.0, these files will be generated or updated in this current
folder. In an analogous way, profile or plot files can only
be loaded if they are located in this current folder. So make
sure that they haven’t been moved to a different folder.
MASTAR
Instructions
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FRONT END PROCESSES
Front End Processes chapter has a variety of
detail and models as supplemental material. Listed below are
the topics and the table models and potential solutions links
associated with these subjects.
Starting materials
Site
Flatness Discussion
Site
Flatness Model
Starting
Materials Potential Solutions Descriptions
Emerging
Materials Discussion
Surface preparation
Surface
Preparation Models
Thermal/thin films,
doping, and etch
Thermal/thin
films models
Thermal/thin
films Potential Solutions Discussion
Gate leakage, specified at 100°C,
is taken to be the same as the transistor subthreshold
leakage at room temperature. This leakage is specified
in the PIDS chapter section on Logic—High Performance
and Low Power Technology Requirements as the off-state
leakage (excluding the junction and the gate leakage components)
at room temperature. Models are provided in supplemental
material.
Off-state
Leakage Models
Doping
models
Lateral
Abruptness of the Source/Drain Extension Paper
Etch
Ferroelectric RAM
FeRAM
Minimum Switching Calculation
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INTERCONNECT
Calculation of the effective k
for various integration schemes
The k values of the bulk dielectric
materials are defined in the dielectric potential solutions
figure and the range of effective k
values for the integrated dielectric stack is listed in the
technology requirements tables. The introduction of these
new low dielectric constant materials, along with the reduced
thickness and higher conformality requirements for barriers
and nucleation layers, is a difficult integration challenge.
Effective
k Calculation
Intra-metal-dielectric
(IMD) Models
Many electrical simulation models exist to extrapolate these
values from well-controlled test structures within a die.
In the supplemental file, simulation extraction results for
representative low-k integration
schemes are presented for several technology nodes. The model
inputs are specific to the ITRS targets for layer thickness,
aspect ratios and dielectric materials projected to be commercially
available concurrent with proposed manufacturing ramp timings.
IMD
Model for Jmax and keff
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FACTORY INTEGRATION
Factory Integration supplemental files
Realizing the potential of Moore’s Law requires taking
full advantage of device feature size reductions, yield improvement
to near 100%, wafer size increases, and other manufacturing
productivity improvements. This in turn requires a factory
that can fully integrate the production equipment that is
the foundation to realizing Moore’s law and the ITRS
with other factory components needed to efficiently produce
the right products in the right volumes on schedule. Preserving
the decades-long trend of 30% per year reduction in cost per
function also requires capturing all possible cost reduction
opportunities. To continue this pace requires the vigorous
pursuit of the following fundamental manufacturing attributes:
maintaining cost per unit area of silicon, decreasing factory
ramp time, and increasing factory flexibility to changing
technology and business needs. The following links provide
more detail regarding the various challenges and requirements
for future semiconductor factories.
The success and market growth of semiconductors
has been driven largely by continuous improvement to cost
per function. Many factors have led to these productivity
gains including process technology shrinks, wafer size changes,
yield improvements, and manufacturing productivity gains.
Fab investment costs continue to increase driven both by the
cost of technology as well as the desire to build larger factories
to get economies of scale.
Moore’s
Law Presentation [including a cost per function model]
Disruptive
Technologies
A semiconductor factory extends
across several manufacturing domains, which include wafer
manufacturing or fabrication, chip manufacturing that involves
probe/e-test, backgrind, and singulation, and finally product
manufacturing where the final package is assembled and tested.
Silicon substrate manufacturing and product distribution are
outside the scope of factory integration. While the integrated
factory must meet the requirements discussed in the ITRS,
these are more easily dealt with if partitioned into five
thrusts, or functional areas, required to perform semiconductor
manufacturing. The five functional thrusts are Factory Operations,
Production Equipment, Material Handling, Factory Information
and Control Systems, and Facilities. Factory Operations, and
its associated factory business model, is a key driver of
requirements and actions for the other five thrusts. Overall,
these five thrusts are used to clarify how difficult challenges
translate into technology requirements and potential solutions.
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ESH
Chemicals, materials and equipment management risk
assessment chemical screening tool
Prior to employing a new chemical or material, it is necessary
to accurately and quickly evaluate the safety, health danger,
and environmental load/impact. A decision is then made whether
to employ the chemical, based on the quantity to be used,
the method to be employed, and the risk assessment. Operator
and maintenance worker exposure to the chemical or material
must be reduced for safety and health reasons, and emissions
must be controlled to minimize environmental load/impact.
In addition, the risk assessment should include a check of
the chemical against the chemical screening tool, to ensure
that the chemical is not banned or under some regulatory watch.
Chemical
Screening Tool Table
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YIELD ENHANCEMENT
Defect target calculator
The random defect targets in Tables 109 and 110 are based
on predefined technology nodes, using data collected by International
SEMATECH member companies on 164 tools, which are divided
into 30 generic tool categories. Even with targets for both
memory and logic products, rarely do actual user circuit line
widths and areas match the ITRS technology node assumptions.
Therefore Wright Williams and Kelly developed a defect target
calculator (Developed by Darren Dance, Wright, Williams, and
Kelly. 1999) to help semiconductor suppliers and manufacturers
compare the roadmap targets to their current or planned needs.
The defect target calculator allows users to enter key technology
parameters and estimate a defect target for a specific chip.
The only parameters required are the Minimum Critical Defect
Size, Random Defect Limited Yield Requirement, Chip Size,
Number Of Mask Levels, and for memory only, the Peripheral
(Logic) Chip Area. This calculator uses the same extrapolation
method as the roadmap tables.
Definitions
- Minimum Critical Defect Size—One
half the user’s Metal 1 pitch for the technology
of interest (nanometers)
- Random Defect limited Yield—Portion
of your yield, which is reduced based on your random defectivity.
Has to be multiplied by the systematic limited yield to
calculate the overall die yield (%)
- Chip Size—The area (critical
or hole die size) of the user’s device (square millimeters)
- Mask Levels—The number
of mask levels in the user’s technology
- Peripheral (Logic) Chip Area—Area
of the layout without redundancy, chip area minus cell
area (%). Only used in the DRAM calculation.
Defect
Target Calculator
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