MARCO GSRC Calibrating Achievable Design Theme

Technology Extrapolation (GTX)

References

Last update: May 31 2000

GTX main reference

• A. Caldwell, Y. Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. Markov, M. Oliver, D. Stroobandt and D. Sylvester, ``GTX: The MARCO GSRC Technology Extrapolation System'', Proc. ACM/IEEE Design Automation Conf., 2000, pp. 693-698.

Model references

• H. B. Bakoglu, ``Circuits, Interconnections, and Packaging for VLSI,'' Addison-Wesley, Chapter 9, 1990.

• D. Sylvester and K. Keutzer, ``Getting to the Bottom of Deep Submicron,'' in Proc. of International Conference on CAD, pp. 203-211, 1998.
• D. Sylvester and K. Keutzer, ``System-Level Performance Modeling with BACPAC -- Berkeley Advanced Chip Performance Calculator,'' in Workshop notes of the 1st Intl. Workshop on System-Level Interconnect Prediction, pp. 109 - 114, 1999.
• D. Sylvester and K. Keutzer, ``Rethinking Deep-Submicron Circuit Design,'' IEEE Computer, pp. 25 - 33, November 1999.

• S. Takahashi, M. Edahiro, and Y. Hayashi, ``A New LSI Performance Prediction Model for Interconnection Analysis of Future LSIs,'' in Proc. ASP-DAC, pp. 51-56, 1998.

• P. D. Fisher and R. Nesbitt, ``The Test of Time: Clock-Cycle Estimation and Test Challenges for Future Microprocessors,'' IEEE Circuits and Devices Magazine 14(2), pp. 37-44, 1998.
• P. D. Fisher, ``Clock Cycle Estimations for Future Microprocessor Generations,'' Proc. IEEE Innovative Systems in Silicon, October 1997.

• Semiconductor Industry Association (SIA), ``National Technology Roadmap for Semiconductors,'' December 1997.

• G. A. Sai-Halasz, ``Performance trends in high-performance processors,'' Proc. of the IEEE, pp. 20-36, Jan. 1995.

• T. Sakurai, ``Closed-form expressions for interconenction delay, coupling, and crosstalk in VLSI's,'' IEEE Trans. Electron Devices, 40, pp. 118 - 124, 1993.

• J. Cong, L. He, C. K. Koh and P. Madden, ``Performance Optimization of VLSI Interconnect Layout,'' Integration, the VLSI Journal, 21, pp. 1-94, 1996.
• J. Cong and D. Z. Pan, ``Interconnect Delay Estimation Models for Synthesis and Design Planning,'' Proc. ASP-DAC, pp. 97-100, 1999.

• User manual.
• J. C. Eble, V. K. De, D. S. Wills and J. D. Meindl, ``A Generic System Simulator (GENESYS) for ASIC Technology and Architecture Beyond 2001,'' in Proc. 9th Annual IEEE Intl. ASIC Conf., pp. 193--196, 1996.
• J. C. Eble III, ``A generic system simulator with novel on-chip cache and throughput models for gigascale integration,'' Ph.D. thesis, Georgia Institute of Technology, 1998.

• Users manual.
• B. M. Geuskens, ``Modeling the Influence of Multilevel Interconnect on Chip Performance,'' Ph.D. thesis, Rensselaer Polytechnic Institute, Troy, New York, 1997.

• P. Raje, ``A Framework for Insight into the Impact of Interconnect on 0.35-um VLSI Performance,'' Hewlett-Packard J., 1995, pp. 1-8.

Other references

• A. B. Babichev, O. B. Kadyrova, T. P. Kahevarova, A. S. Leshchenko and A. L. Semenov, ``UniCalc, A Novel Approach to Solving Systems of Algebraic Equations,'' Interval Computations, N2, pp. 29 - 47, 1993.

• V. V. Telerman, V. A. Sidorov, D. M. Ushakov, ``Problem Solving in the Object-Oriented Environment NeMo+,'' in Perspectives of System Informatics (PSI-96), pp. 91 - 100. Berlin: Springer, 1996. (Lecture Notes in Computer Science, vol. 1181).

• M. J. Buckley, K. W. Fertig, and D. E. Smith, ``Design Sheet: An Environment for Facilitating Flexible Trade Studies During Conceptual Design,'' in 1992 Aerospace Design Conf., 1992.
• S. Y. Reddy and K. W. Fertig, ``Design Sheet: A System for Exploring Design Space,'' in Proc. Artificial Intelligence in Design, pp. 347 - 366, 1996.