MARCO GSRC Calibrating Achievable Design Theme

GTX: GSRC Technology Extrapolation

Contributions to GTX

Andrew B. Kahng, Farinaz Koushanfar, Hua Lu and Dirk Stroobandt
Last update: Dec 17 2001

Introduction

We encourage you to use GTX for evaluating, emulating, or comparing between existing estimation methods, and especially to use it as a development tool for new models and methods. If you would like to share your methods with other users (which we strongly encourage), please take a moment to submit your parameter files, rule files and rule chain files to gtx@vlsicad.ucsd.edu (how to contribute). We will check consistency with other GTX models and add them to this page.

Referencing

Users of GTX presenting results obtained through GTX should at least refer to the GTX website and to the references corresponding to used models that are provided by the contributors of those models. The GTX system has been described in a DAC 2000 paper which is the primary reference for the GTX system.

Contributions

We strongly encourage contributions of "open-source" models. Current open-source contributions are

Model Contributor Contribution Contact
Cycle time UCLA VLSI CAD lab (vlsicad.cs.ucla.edu) with help from Dennis Sylvester BACPAC (zip) (tar-gz) GTX group
UCLA VLSI CAD lab (vlsicad.cs.ucla.edu) with help from Phil Fisher Fisher (zip) (tar-gz)
UCLA VLSI CAD lab (vlsicad.cs.ucla.edu) SUSPENS (zip) (tar-gz)
Takahashi (zip) (tar-gz)
Device model Dennis Sylvester and Kevin Cao (www.eecs.berkeley.edu/~dennis/) SOI and Bulk Si devices (zip) (tar-gz) Yu (Kevin) Cao, GTX group
Gate and interconnect delay model Kevin Cao, Xuejue Huang, Sudhakar Muddu, Dennis Sylvester (www.eecs.berkeley.edu/~dennis/) Gate and interconnect delay model (zip) (tar-gz) Yu (Kevin) Cao, GTX group
Power requirement for low power device model UCLA VLSI CAD lab (vlsicad.cs.ucla.edu) and UCSD VLSI CAD lab (vlsicad.ucsd.edu) STRJ (zip) (tar-gz) GTX group
Low-cost, low-power SOC design productivity and cost model Productivity (zip) (tar-gz)
Active area and gate area model ORTC_ActiveArea (zip) (tar-gz)
Design ITWG inputs to ORTCs ITWG_inputs (zip) (tar-gz)
Process Integration Devices and Structures (PIDS) PIDS (zip) (tar-gz)
Overall Technology Roadmap Characteristics (ORTC) ORTC (zip) (tar-gz)