User Documentation for Studies in GTX

• Berkeley Advanced Chip Performance Calculator (BACPAC)
• Clock Cycle Estimation for Future Microprocessors (Fisher)
• Stanford University System Performance Simulator (SUSPENS)
• A New LSI Performance Prediction Model (Takahashi)
• Deep Sub-Micron Bulk and SOI MOSFET Device
• Critical Path Delay and Noise Estimation
• UCSC SiP Internal IO Interface Model (SCIO)
• Analytical Interconnect Parasitics and Performance Models
• Active Area and Gate Area (ORTC_ActiveArea)
• Design ITWG inputs to ORTCs
• Process Integration Devices and Structures (PIDS)
  
• Overall Technology Roadmap Characteristics (ORTC)

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