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International Technology Roadmap for Semiconductors
ITWG / IRC Working Meeting
Grenoble, France
25-28 April 2001
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2001 Timing and Chip Size Model [Sc. 3.7] Emerging Devices
Design
Test
Process Integration
Front End Processes Lithography
Interconnect
Factory Integration
Assembly & Packaging Environment, Safety & Health
Defect Reduction
(compressed file version, this file will extract as a PowerPoint file)
Metrology
Modeling & Simulation
 
The ITRS is devised and intended for technology assessment only and is without regard
to any commercial considerations pertaining to individual products or equipment.